The objectives of this WP are:
- Specification, design and wafer or chip-level characterization of high performance PICs for WDM coherent and direct detection applications
- Design and fabrication of 4-electrical Channel >60 GBaud QAM-16 modulator drivers and TIAs for use in coherent PICs
- Packaging of WDM coherent- and direct-detection transceivers prototypes on evaluation boards that allow testing at speeds of 60 Gbaud with low loss optical coupling
- Preparation of packaging protocols that guide scaling of transceiver manufacture to volume using standards module form factors, such as QSFP pluggable modules
- Performance evaluation of two PIC transceivers: 4λ x 100Gb/s PIC for short reach direct detection applications and 1λ x 400Gb/s PIC with a tunable laser for wideband IP-transport and IP-routing coherent-detection applications.
- Task 4.1: Specification, design, and characterization of high performance PICs (III-V Lab leader, CEA, imec, Tyndall, Argotech, Nokia) (M1-M30)
Electrical and optical specifications will be provided by Nokia for the PIC design, in particular for the choice of the building blocks. Target values in terms of BER (minimum 10-4 for short-reach and 10-2 for coherent), required optical output power level and maximum electrical power consumption will be defined in detail. Choice of modulation formats: PAM4 or DMT for short-reach, targeted reach, operating wavelength range and device-specific parameters will be clarified (for instance the spectral linewidth, output power, RIN level of lasers / modulator bandwidth / losses in passive optical devices / fiber coupling technology / responsivity of photodiodes). Maximum power consumption values, thermal management and physical dimensions of the developed PICs should potentially meet requirements defined in standard telecoms operating environmental conditions and multi-source agreements for packaging. Following those specifications, and the inputs from WP2 on hybrid III-V/Si building blocks, the two types of the transceiver PICs will be designed in this task by III-V Lab and the fabrication will be done in WP1 by CEA. Those PICs will contain also passive elements such as wavelength multiplexer and de-multiplexer, polarization splitter and combiner. Those passive elements will be designed by III-V Lab and CEA on the silicon photonics platform without any change on the fabrication process. The first fabrication run of the preliminary PICs will be made on the same mask as the second run of the building blocks, while a special dedicated run will be devoted to the final PICs. For the second run of the complete final PICs, the mask layout will be provided by III-V Lab. The silicon wafers will be fabricated by CEA, and several types of III-V wafers will be provided by III-V Lab. Multi-die to wafer bonding will be performed by CEA, and the III-V back-end process will be made on the 200 mm R&D CMOS line in WP1. Copper pillars will be prepared on those wafers in order to be connected with the EICs. The fabricated PICs will be characterized at CEA and III-V Lab. Samples will be selected by CEA and sent to Tyndall for packaging.
- Task 4.2: Design, fabrication and evaluation of 60GBd linear drivers and TIAs for complex modulation formats (IMEC leader) (M01-M30)
Within this task, IMEC will design and characterize the dedicated high-speed low-power consumption linear IIIV/ Si hybrid modulator driver and TIA arrays of PICTURE. This task will study various issues (such as linearity, interconnect parasitic, impedance matching, AC/DC coupling, single-ended/differential driving, floor planning and thermal performance) and innovative approaches related to the co-design and co-optimization of the photonic – electronic circuitry. A suitable technology will then be selected for the electronic circuit design based on the detailed specifications.
In the transmitter, Feed-Forward Equalization (FFE) may be considered to overcome any bandwidth limitation e.g. due to excessive parasitic. Interacting with task T2.2, electronic/photonic co-design allows to abandon the classic 50Ω termination and/or characteristic of the TW-electrodes, resulting overall optimized performance in terms of power consumption and signal bandwidth. In the receiver, automatic gain control will be implemented to achieve a high sensitivity with a sufficiently high linearity. High sensitivity TIA architectures will be studied taking into account the photodiode parameters, interconnect parasitic between PD and TIA and crosstalk issues of the TIA arrays based on 3D electromagnetic field simulations. The work within this task involves the design of 4-channel 60 GBaud QAM-16 modulator drivers and TIAs, targeting >45GHz bandwidth, 1.5Vpp drive strength and total 3.5 pJ/bit power efficiency.
The required substrates and test boards for chip-level testing will also be designed. The fabricated chips will be first characterized at IMEC and then used for integration in Task 4.3.
Figure 1. An example of IMEC’s integrated coherent receiver (ICR) [J. Verbist et al., 2016, DOI: 10.1109/LPT.2016.2582799]
- Task 4.3: Design and Assembly of overall transceiver package prototypes with or without full co-integration of PIC/ EIC (Tyndall leader, III-V Lab, CEA, imec, Argotech) (M1-M32)
This task will take account of the key photonic and electronic design parameters to ensure the overall assembly is designed for cost-effective packaging that can be scaled to volume manufacture. Critical package design parameters include; electrical bond-pad layout and pitch, RF transmission lines, fibre coupling layout and general loor-plan of both photonic and electronic chips. These package design parameters will ensure the chip-scale assembly is also compatible with the overall system package, including optical and electrical connector components.
The information gained in tasks 4.1 and 4.2 will be used to prepare a full design specification for the overall transceiver package for both the short-reach and Coherent transceivers. The packages will be designed to ensure optimum optical coupling, RF electrical performance and efficient thermal management (ideally based on passive thermal control). Key packaging process steps include, fibre coupling, flip-chip integration of the electronic and photonic devices, high speed RF interposer design, assembly of the 3D assembled photonic-electronic devices on the RF interposer, integration of the subassemblies on RF-PCB, and assembly of the combined sub-systems in a full transceiver mechanical housing that ensures efficient thermal control of the transceiver modules. The table displayed under Part B section 3.1 "Graphical information referred to in work package description tables of Part A" shows the different prototypes to be made during PICTURE project.
Based on the packaging processes developed in this task, a protocol will be prepared to enable scale-up of the packaging process to high volume. This task will not only receive inputs from the previous tasks, but will also provide input to those tasks, ensuring they are designed for volume manufacturing. Project partners Tyndall and Argotech have significant expertise transferring processes developed from prototype development to volume manufacture, and this experience will be used to help prepare this protocol.
Figure 2. Wire bonding tests have already been performed by Argotech on IMEC EICs. Ball-wedge and ball-stitch-on-ball methods.
- Task 4.4: System assessment of PICs (Nokia leader, III-V Lab, imec, Tyndall) (M20-M36)
The packaged devices from task 4.3 will be tested in Nokia Bell Labs France over short-distance and metro/long-haul transmission systems. A first series of PIC modules will be tested (short-reach PIC and coherent PIC without EIC) from M23. Performance will be assessed in terms of BER curves versus received optical power or signal-to-noise ratios, as well as in terms of power consumption and will be summarized in a report.
For the short-reach applications, various modulation formats will be considered, namely 60GBaud PAM4 and DMT. 100Gb/s channel performance will be assessed in a back-to-back configuration and over a few kilometers long SSMF link. BER and SNR after equalization will be measured for various receiver power levels and various digital equalizer structures. Important parameters such as Vπ and 3dB-bandwidth of the modulator, and linewidth of the laser will also be evaluated at III-V Lab and Nokia.
For the long-haul coherent transceiver PIC, back-to-back tests will also be done, followed by transmission tests over a WDM experimental setup comprising a few hundred kilometers of SSMF. BER curves and SNR after equalization will also be measured for various OSNR levels at the receiver. Moreover, an important aspect that will be evaluated for this PIC is the easy control of the different bias voltages (there will be 6 bias voltages for the PDM I/Q modulator, andan additional bias for the MOSCAP junction of each modulator arm, as well as DC sources for the tunable laser, SOA, photodiodes, and thermo-electrical cooler).
The performance of a second generation of the packaged modules will be assessed from M32. Similar tests will be done over this new generation PICs as the previous one. Control of the new electronic blocks (driver and TIA) for the coherent PICs will be evaluated.
Figure 3. Diagram of the experimental setup for the performance assessment of the packaged PIC modules