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  • Work package number WP2 Lead beneficiary - III V LAB GIE
  • Work package title Hybrid III-V/Si building blocks for PICs
  • Start month 1 End month 30 

Objectives

The objective of WP2 is to design and characterize the building blocks such as lasers, modulators and photodiodes based on the heterogeneous integration of III-V on silicon. This WP will also take in charge the back-end fabrication of bonded III-V dies on silicon. The detailed targets are:

  1. Design and fabrication of a wavelength tunable DFB lasers with tuning range of 2 nm, and output power level > 10 dBm
  2. Design and fabrication of a SOA with single pass gain > 15 dB and output saturation power > 13 dBm
  3. Design and fabrication of a modulator with VpLp< 1.5 V.mm, losses < 2 dB/mm, 3 dB modulation bandwidth > 35 GHz
  4. Design, fabrication and test of photodiode with sensitivity > 0.8 mA/mW and modulation bandwidth > 35 GHz The optimized building blocks will be used in WP4 for the final PIC demonstrators.

Description of work and role of partners

WP2 - Hybrid III-V/Si building blocks for PICs [Months: 1-30]

III V LAB GIE, SOUTHAMPTON, CEA, IMEC

  • Task 2.1 – Hybrid III-V/Si lasers and amplifiers (III-V Lab Leader, CEA)

In this task, the objective is to develop wavelength tunable DFB lasers (see state-of-the-art DFB in fig. 1), widely wavelength tunable lasers (fig. 2 & fig. 3) and also high power SOAs (fig. 4).

Modelling works will be carried out first to determine the silicon waveguide geometry, the Bragg grating pitch, etching depth, etc. Special attention will be paid to the taper between III-V and silicon waveguides. The MOS capacitive structure will be introduced inside the DFB laser (see state-of-the-art DFB in fig. 1) in order to achieve the wavelength tuning. For the widely wavelength tunable laser, ring resonators will be introduced inside the laser cavity. The heating on those resonators will allow to achieve the wavelength tuning. For the SOA design, the silicon waveguide width underlying the III-V waveguide will be engineered to enhance the output saturation power and keep the required single pass gain.

Fig.1. III-V / Si hybrid DFB laserFig.1. III-V / Si hybrid DFB laser

Fig.2. Bird view structure of a III-V / Si hybrid tunable laserFig.2. Bird view structure of a III-V / Si hybrid tunable laser

Fig.3. Optical spectra from a III-V / Si hybrid tunable laser, designed, fabricated and tested in III-V LabFig.3. Optical spectra from a III-V / Si hybrid tunable laser, designed, fabricated and tested in III-V Lab

Fig.4. III-V / Si hybrid SOA: left hand side: bird view and vertical stack structures, with views of optical modes at different points of the device waveguide; right hand side: optical gain spectra obtained from such a SOAFig.4. III-V / Si hybrid SOA: left hand side: bird view and vertical stack structures, with views of optical modes at different points of the device waveguide; right hand side: optical gain spectra obtained from such a SOA

The mask layout of the first run will be provided by III-V Lab to CEA at M3 and the second one at M13. The back-end process involving III-V structuring and metallization will be made by III-V Lab and the final testing will be made by both CEA and III-V Lab.

  • Task 2.2 – Hybrid III-V/Si capacitive modulators (SOTON Leader, III-V Lab, CEA, imec)

The main objective of this task is to develop capacitive hybrid III-V/Si modulators. In parallel, silicon MOSCAP modulators will also be designed and fabricated to carry out a technical comparison.

Modelling will be carried out to determine the optimum design of both capacitive devices, to evaluate the modulation efficiency, and the insertion loss as the primary design parameters, along with modulation bandwidth. To achieve the targeted high bandwidth >35 GHz, modulator designs will be based on travelling-wave electrode (TWE) will be explored (Figure 15), where the electrical signal co-propagates with the optical signal to overcome intrinsic RC limitation. Since lumped electrode model is not valid any more, co- simulation/design of driver with distributed electrode and modulator parasitics is essential to achieve maximum electro-optical bandwidth. Key issues to be addressed are dielectric and conductor losses at microwave frequencies, impedance matching, transmission line topologies, and velocity mismatch between electrical and optical signals.

Modelling of the III-V devices will be carried out by CEA and III-V Lab, and the silicon devices will be designed and modelled by SOTON. CEA and III-V Lab will fabricate the III-V devices in a collaborative effort, and SOTON will fabricate the silicon devices.

Moreover, a systematic investigation will be made through simulation and also characterization on fabricated samples in WP1 to determine which type of n-doped III-V layers enables to achieve the maximum refractive index change with respect to the carrier density change. This works will be mainly carried out by III-V Lab.

Imec will propose novel electrode design for the travelling wave type MOS modulators. Co-optimization with driver EIC will be made in order to push the modulation bandwidth to more than 35GHz.

High speed testing of all devices will be carried out by SOTON, CEA and III-V Lab. The optimal devices will be selected for inclusion into the final transceiver designs in WP4. Individual device developments will be completed by 24 months.

  • Task 2.3 – Hybrid III-V/Si photodiodes (III-V Lab Leader, CEA)

In this task, the objective is to develop high sensitivity and large bandwidth hybrid III-V/Si photodiodes.

Contrary to the laser, the light will not travel back and forth between III-V and silicon waveguides. Consequently, no adiabatic taper is needed for the coupling between III-V and silicon waveguides. Modelling work will be carried out first to determine the silicon waveguide geometry, and also the III-V waveguide geometry in order to achieve high sensitivity and large modulation bandwidth. The first mask layout will be provided by III-V Lab to CEA at M3 and the second one at M13. The back-end process involving III-V structuring will be made by III-V Lab and the final testing will be made by both CEA and III-V Lab.

Project Support

III-V Labs
Campus de Polytechnique
1, avenue Augustin Fresnel
F-91767 Palaiseau Cedex
Phone : + 33 1 69 41 55 00
Arnaud Wilk 
arnaud.wilk@3-5lab.fr

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