Menu

COVID-19

To tackle COVID-19 European governments are imposing restrictions on our daily activities for the foreseeable future. As individuals, and as a community, we have a shared responsibility to follow the latest public advice as strictly as possible to tackle the spread of COVID-19. 
At a time of global crisis, the  PICTURE consortium  is rising to the challenge. We are now working from home and most of our laboratories and clean room complexes are closed. 
It is not business as usual but our business does not stop.
We have a unique opportunity to think, to progress our work via innovative design and modelling, to write papers , and to use digital technology to engage with the community in innovative ways. Our operations have swiftly migrated online and we will update our partners and collaborators on effective ways of working with us as appropriate.
We are proud of the fact that over many decades our contributions to the global internet are helping keep the world running through this difficult time. It is a timely reminder that connectivity provides resilience and we are redoubling our efforts to ensure that that the next generation of optoelectronic hardware is available when we need it.
We are enormously grateful to our sponsors and staff for bearing with us in these difficult times. Your generous support and positive energy ensure our community continues to thrive.

  • Work package number WP1 Lead beneficiary - CEA
  • Work package title Heterogeneous integration using a thin bonding layer
  • Start month 1 End month 30

The objective of WP1 is to develop the technology to build Silicon PICs based on hybrid III-V/Si components on 200 mm wafer line. Technological developments will include the control of a thin bonding layer after SOI processing for wafer, die and multi-die bonding. In addition, optimized QW and QD epitaxial stacks will be developed for lasers, modulators and photodetectors with surface characteristics compatible with wafer bonding.

Based on these technological developments and the designs of WP2 and WP4, high-performance hybrid III-V on Si building blocks and photonic integrated circuit demonstrators will be abricated for on-wafer test, packaging and assessment in WP4.

Description of work and role of partners

WP1 - Heterogeneous integration using a thin bonding layer [Months: 1-30]

CEA, III V LAB GIE, UCL

  • Task 1.1 – Development of thin bonding technology (CEA Leader) (M1-M24)

In this task, the objective is to develop a thin bonding layer of 5-10 nm after the processing of the SOI levels. The thickness should be very uniform over a 200 mm wafer, with a rms less than 2 nm. In the classical hybrid laser process, the silicon structures are encapsulated with SiO2 with a subsequent CMP step to leave a planar SiO2 layer of about 75 to 100 nm on top of the Silicon waveguides. In this task, CEA will explore several CMP strategies, including CMP stop on the top of the Si waveguides or the use of a SiN CMP stop layer. An alternative approach without the SiO2 encapsulation and CMP step is based on thermal oxidation of the silicon guiding layers. All those approaches are explained schematically in figure below.

Technological strategies for III-V to Si bonding with thin bonding layerTechnological strategies for III-V to Si bonding with thin bonding layer

These developments will start at the beginning of the project with already available patterned SOI wafers in order to select the best strategy.

  • Task 1.2 – Bonding-compatible epitaxy of optimized III-V laser, modulator and photodiode stacks (III-V Lab Leader, UCL) (M1-M17)

In this task, III-V Lab will design and fabricate InP-based stacks with QW layers for both 1.3 μm and 1.5 μm for

lasers, modulators and photodiodes. Each building block will be optimized separately for multi-die bonding. Particular attention will be paid on the quality of the top surface in order to assure a low defect density enabling high bonding yield. Typically, the defect density should be less than 0.8 cm-2 for the defect size larger than 40 μm. UCL will provide high surface quality GaAs-based wafers and III-V Lab InP-based wafer for bonding in order to prepare the GaAs/SiO2/Si and InP/SiO2/Si templates to be used in WP3. Those GaAs and InP wafers should have also high surface quality and contain an etch-stop layer such that the substrate of the bonded wafers can be removed through wet etching. 

  • Task 1.3 –SOI process and III-V/SOI bonding for building blocks and regrowth on templates (CEA Leader) (M4-M26)

The objective of this task is to fabricate SOI wafers containing the silicon circuits designed in WP2 and subsequently proceed to the bonding of III-V wafers and heterogeneous III-V dies using the optimized process developed in Task 1.1.

SOI wafers containing the bonded multi-III-V dies will be delivered by CEA to III-V Lab for III-V process and metallization, planned in WP2.

CEA will also perform the bonding of GaAs and InP wafers on SOI wafers containing all necessary silicon waveguides and doping for WP3. Regrowth on those templates and subsequent III-V process will be carried out by UCL on GaAs/ SiO2/Si templates and by III-V Lab on InP/SiO2/Si template in WP3.

Schematic illustration of hybrid III-V/Si integration 200mm process using multi-die to wafer bondingSchematic illustration of hybrid III-V/Si integration 200mm process using multi-die to wafer bonding

  • Task 1.4 - SOI/Bonding/III-V process of PICs with thin wafer bonding (CEA Leader) (M4-M30)

The objective of this task is to fabricate the two types of PICs: short reach direct detection WDM transceiver operating at 1.3 μm and long reach coherent transceivers operating at 1.55 μm. The design and the mask layouts will be made in WP4 by III-V Lab.

As in Task 1.3, CEA will take in charge the SOI fabrication of PICs, the thin layer bonding of III-V multi-dies. The III-V and metallization process will be directly made on the CEA’s 200 mm process line to demonstrate the high performance, high yield and the industrial manufacturability of the PICs on a full 200 mm platform (see figure above).

Project Support

III-V Labs
Campus de Polytechnique
1, avenue Augustin Fresnel
F-91767 Palaiseau Cedex
Phone : + 33 1 69 41 55 00
Arnaud Wilk 
arnaud.wilk@3-5lab.fr

Quick Links

  • Picture-h2020 Project Intranet
  • Silicon Photonics Group website
  • Picture-h2020 Events